module ram_rw(
    input sys_clk,
    input sys_rst_n,
    input wire[7:0] douta,

    output reg wea,
    output reg [4:0] addra,
    output reg [7:0] dina,

    output reg [7:0] out_data
);

parameter CNT_MAX = 6'b11_1111;
reg [6:0] cnt;

// 计数器计�??
always@(posedge sys_clk or negedge sys_rst_n)begin
    if(!sys_rst_n)
        cnt <= 7'b0;
    else if (cnt < CNT_MAX)
        cnt <= cnt + 7'b1;
    else
        cnt <= 7'b0;
end

// 读写控制
always@(posedge sys_clk or negedge sys_rst_n)begin
    if(!sys_rst_n)
        wea <= 1'b0;
    else if(cnt < 7'd32)
        wea <= 1'b1;    // �??
    else
        wea <= 1'b0;    // �??
end

// 地址
always@(posedge sys_clk or negedge sys_rst_n)begin
    if(!sys_rst_n)
        addra <= 5'b0;
    else if(cnt < 7'd32)
        addra <= cnt[4:0];
    else if(cnt < 7'd64)
        addra <= cnt[4:0];
    else
        addra <= 5'b0;
end

// 写数�??
always@(posedge sys_clk or negedge sys_rst_n)begin
    if(!sys_rst_n)
        dina <= 8'b0000_0000;
    else if(cnt < 7'd16)
        dina <= cnt;
    else if(cnt < 7'd32)
        dina <= cnt;
    else
        dina <= 8'b0000_0000;
end

// 读数�??
always@(posedge sys_clk or negedge sys_rst_n)begin
    if(!sys_rst_n)
        out_data <= 8'b0000_0000;
    else if(wea)
        out_data <= 8'b0000_0000;
    else
        out_data <= douta;
end

endmodule